PYXIS
Team members:Ìý
- April Lewis
- Aaron Martin
- Steven Sherk
he objective is to build a general purpose microprocessor using the XCV300 FPGA board and Verilog. The 16 bit RISC will be created using MIPS design as a foundation. The processor will use state machine principles: fetch, decode, execute, read, and write to execute the instruction and data code. The processor will contain the following major components: controller, memory, instruction register, data registers, and an ALU. User interfaces will consist of Monitor/LCD and Keypad/keyboard.
We will create our own reduced instruction set and develop an assembler to convert the assembly code to machine language. The assembler will be written in C and executed on a PC. EPROM or EEPROM, and SRAM will be used to store the code necessary to test the microprocessor.
Test code could include a word game like scrabble, an output to a piece of hardware like a speaker or motor, or code that tests the performance of the processor design. For demonstration, a monitor could be used to display graphics that we design in our own assembly language or higher level mystery language.
Some possible design features include the following:
- 5 Stage Pipeline design
- L1 Data Cache and Instruction Cache
- Divider
- Floating Point Unit
- C Compiler