None
Team members:
- Thomas Bozic
- Ian Nuber
- Greg Ramsey
- Henry Romero
- Matthew Unangst
Our group proposes to design and implement a pipelined 32-bit "softcore" processor featuring a MIPS-like instruction set. We will implement the processor in structural Verilog on a Xilinx FPGA. The processor will also require the use of certain off-chip devices. These devices include random access memory, read only memory, 16-button keypad, hardware interrupt handler, and a simple LCD. All of these modules will be integrated onto a custom designed printed circuit board (PCB), which we will wire wrap to the FPGA board.
The design process will begin with defining the interface file between the fundamental units of the processor. Such units include the program counter, register file, control logic, main memory, and the arithmetic logic unit. We will also need to design a higher level mapping which details the interactions between these functional units. This mapping will also need to account for the pipeline design. Once we have a clearer understanding of the workings of the processor, we will begin programming the functional units in Verilog, define the instruction set, and start on the assembler. Shortly thereafter, we will begin prototyping the off-chip PCB with a wire-wrapped design. At this point, all essential functional units will be implemented in the FPGA via Verilog and the assembler will also be complete. After the prototype begins to work efficiently, we will order our first PCB design. While waiting for the PCB, we will begin executing our secondary objectives for the project. Our secondary objectives include designing a simple compiler, I/O interfaces, Capstone Expo demo, and floating point unit. We are hoping the processor will be fully functional two weeks before the Capstone Exposition date, which provides the group with a buffer for unexpected set backs.