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Aztec

Three of the members of Aztec

Team members:

  • Jed Brown
  • Mike Mason
  • Josh Price
  • Andrew Youngs

We are designing a PC Oscilloscope for our capstone project. The design objectives for our oscilloscope are:

  • Probe functions as contact from DUT to oscilloscope.
  • Signal goes through probe into the signal conditioner.
  • The signal conditioner readies the signal for the ADC
  • The Analog/Digital Converter converts signal it to digital..
  • The FPGA then takes that data and places it into memory.
  • Once memory is full, data is sent to the USB controller (handled by the fpga) via UART.
  • The USB control sends data to the PC.

There are two ways the scope could be used.

  • Trigger based
  • Free-flow

For trigger base, via software we tell the FPGA when we want it to trigger (at what voltage), when the data received hits that value, the process above starts and data is sent to the memory.

For free-flow as soon as the ADC passes valid data to the FPGA, we begin passing the data to the memory and to the USB in a loop until via commanded to stop.

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